As is known, charge pump circuits are widely used in a wide range of electronic applications to obtain output voltage values higher than a given input voltage (basically operating as DC-DC boost converters), exploiting the use of capacitors as charge-accumulation elements. For example, charge pump circuits are used in flash-memory devices for generating the high voltage values required for performing data reading, writing, and erasing operations, starting from the low values of the internal supply voltage (the so-called “logic supply voltage Vdd”, with values, for example, comprised between 1 V and 1.35 V, for CMOS flash-memory devices in 90-nm technology).
In particular, charge pump circuits of a latch type (also known as “latch circuits”) have been proposed, operating with just two enabling signals (or phase signals) and using only low voltage transistors (having, for example, a maximum sustainable voltage comprised between 1 V and 1.35 V). These circuits are thus able to operate at high frequencies, for example of the order of 100 MHz (unlike common four-phase charge pump circuits, capable of reaching at most frequencies of 10-50 MHz).
In brief, and as shown in FIG. 1, a two-phase charge pump latch circuit, designated as a whole by 1, has an input terminal IN, on which it receives the logic supply voltage Vdd (in particular, a supply voltage with logic values), and an output terminal OUT, on which it supplies the boosted output voltage Vout, for a load (schematically represented as the parallel connection of a load capacitor CL and a current generator IL).
The charge pump circuit 1 comprises a plurality N of stages S1, . . . , SN, cascaded between the input terminal IN and the output terminal OUT, each receiving a first low voltage phase signal FX and a second low voltage phase signal FN, having negated (or complementary) values with respect to one another. An intermediate node INT is present between two successive stages in the charge pump circuit 1 (the intermediate node INT hence corresponding to the output of the previous charge pump stage Si−1, and to the input of the next stage Si). The low voltage phase signals FX, FN have, for example, logic values equal to 0 (or ground, GND) or to Vdd, and are generated by an appropriate generator circuit (not illustrated).
Each stage S1, . . . , SN comprises a first pump capacitor Cu and a second pump capacitor Cd, receiving the first low voltage phase signal FX or the second low voltage phase signal FN (it should be noted that the arrangement of the phase signals is reversed from one stage to the next; i.e., if the first pump capacitor Cu of a given stage receives the first low voltage phase signal FX, the corresponding first pump capacitor Cu of the immediately preceding stage and immediately subsequent stage receives the second low voltage phase signal FN). The first and second pump capacitors Cu, Cd are moreover connected, respectively, to a first internal node U1, . . . , UN and to a second internal node D1, . . . , DN.
Each stage S1, . . . , SN further comprises a latch circuit L1, . . . , LN, comprising a pair of NMOS latch transistors (of a low voltage type) and a pair of PMOS latch transistors (which are also of a low voltage type), the control terminals of which are appropriately connected to the internal nodes U1, . . . , UN, D1, . . . , DN, so as to provide switches designed to enable selective and alternate transfer of the charge accumulated in the pump capacitors Cu, Cd from one stage to the next (these transistors are for this reason commonly referred to as “pass transistors”).
In particular, it may readily be appreciated that the arrangement of the transistors in the latch circuits L1, . . . , LN is such as to perform transfer of charge between the first pump capacitors Cu of successive stages, in a first half-period (in which the first low voltage phase signal FX is high, for example equal to Vdd, and the second low voltage phase signal FN is low, for example equal to 0 V), and to perform transfer of charge between the second pump capacitors Cd of successive stages, in a second half-period (in which the first low voltage phase signal FX is low and the second low voltage phase signal FN is high), thus guaranteeing the voltage-boost effect between the input terminal IN and the output terminal OUT. The first and second half-periods refer, for example, to a common periodic synchronisation signal (or clock signal).
Moreover, it may be appreciated that the voltage on the intermediate node INT remains practically constant during the entire operating period of the charge pump circuit.
To improve the performance of the aforesaid charge pump circuit of a latch type, in particular in operating conditions with very low values of the supply voltage (i.e., for limit values lower than the logic supply voltage Vdd, for example, 1 V), in patent application No. EP-A-1 881 589 an improved circuit has been proposed, as shown in FIG. 2 (which, for simplicity of illustration, refers to a single pair of consecutive stages Si−1, Si of the charge pump circuit, which is once again designated by the reference number 1).
In detail, each charge pump stage Si−1, Si comprises once again a first pump capacitor Cu and a second pump capacitor Cd, receiving respective low voltage phase signals FX, FN, complementary to one another, and are connected to a respective internal node Ui−1, Ui and Di−1, Di. Each charge pump stage Si further comprises a latch circuit Li−1, Li with suitable transistors operating as switches (or pass transistors). For simplicity of illustration, only the transistors involved in the transfer of charge between the charge pump stages Si−1, Si, in particular between the respective first pump capacitors Cu or second pump capacitors Cd are represented in FIG. 2 (it being altogether evident that similar transistors are, however, present for transfer of charge with respect to the immediately preceding and subsequent stages).
In particular, a first latch transistor MpU, of a low voltage PMOS type (here shown only in the charge pump stage Si−1) is connected between the internal node Ui−1 and an intermediate node INT (set between the consecutive charge pump stages Si−1 and Si), and has a gate terminal connected to a first control node PgU; a second latch transistor MpD, of a low voltage PMOS type (in the same charge pump stage Si−1) is connected between the internal node Di−1 and the intermediate node TNT, and has a gate terminal connected to a second control node PgD; a third latch transistor MnU, of a low voltage NMOS type (herein shown only in the charge pump stage Si) is connected between the internal node Ui and the intermediate node INT, and has a gate terminal connected to a third control node NgU; and a fourth latch transistor MnD, of a low voltage NMOS type (in the same stage Si of the charge pump circuit 1) is connected between the internal node Di and the intermediate node INT, and has a gate terminal connected to a fourth control node NgD.
It should be noted that, for the purposes of operation of the charge pump circuit, the distinction between the drain and source terminals of the various MOS transistors is not important so that they can be referred to generically as “current-conduction terminals”.
Moreover, as highlighted previously, it is evident that each latch circuit Li−1, Li further comprises latch transistors for charge sharing with the adjacent stages. For example, the latch circuit Li further comprises, downstream of the internal node Ui PMOS latch transistors altogether similar to the first and second latch transistors MpU, MpD.
The charge pump circuit 1 further comprises a stabilization stage 2, which is set between each consecutive pair of charge pump stages Si−1, Si, and generates appropriate control signals for the gate terminals of the transistors of the latch circuits Li−1, Li. The stabilization stage 2 comprises: a first biasing unit 2a for biasing the gate terminals of the latch transistors MpU and MpD of the charge pump stage Si−1; and a second biasing unit 2b for biasing the gate terminals of the latch transistors MnU and MnD of the charge pump stage Si.
In detail, the first biasing unit 2a comprises: a first biasing capacitor Cb1, having a first terminal receiving the low voltage phase signal FX and a second terminal connected to the second control node PgD; a second biasing capacitor Cb2, having a first terminal receiving the low voltage phase signal FN and a second terminal connected to the first control node PgU; a first control transistor Mp1, of a low voltage PMOS type, which is connected between the intermediate terminal INT and the second control node PgD, and has its gate terminal connected to the first control node PgU; and a second control transistor Mp2, of a low voltage PMOS type, which is connected between the intermediate terminal INT and the first control node PgU, and has its gate terminal connected to the second control node PgD.
Likewise, the second biasing unit 2b comprises: a third biasing capacitor Cb3, having a first terminal receiving the low voltage phase signal FX and a second terminal connected to the third control node NgU; a fourth biasing capacitor Cb4, having a first terminal receiving the low voltage phase signal FN and a second terminal connected to the fourth control node NgD; a third control transistor Mn1, of a low voltage NMOS type, which is connected between the intermediate terminal INT and the third control node NgU, and has its gate terminal connected to the fourth control node NgD; and a fourth control transistor Mn2, of a low voltage NMOS type, which is connected between the intermediate terminal INT and the fourth control node NgD, and has its gate terminal connected to the third control node NgU.
In general, the pump capacitors Cu, Cd may have a same first nominal capacitance; likewise, the first, second, third, and fourth biasing capacitors Cb1, Cb2, Cb3 and Cb4 may have a same second nominal capacitance. The voltage Vint on the intermediate node INT, which remains substantially constant for the entire operating period, is used by the biasing stage 2 for correctly driving switching-on and switching-off of the pass transistors in the latch circuits Li−1, L1.
In detail, it is possible to distinguish the two following operating conditions, equivalent to one another, respectively in a first half-period and in a second half-period of the clock signal:                FN=Vdd, FX=0: V(Di−1) (it should be noted that V(D) and V(U) are the voltages at the corresponding nodes D and U) goes to a high value and V(Ui−1) goes to a low value; likewise V(Di) is at a low value, while V(Ui) is at a high value; in this case, the first control node PgU goes to a high value (equal to Vint), whereas the second control node PgD goes to a low value (in particular, it decreases by a value equal to the logic supply voltage Vdd with respect to Vint), thus enabling switching-on of the second latch transistor MpD and switching-off of the first latch transistor MpU; in the same half-period, the fourth control node NgD goes to a high value (higher by a value equal to the supply voltage Vdd with respect to Vint), and the third control node NgU goes to a low value; consequently, the fourth latch transistor MnD switches on, whereas the third latch transistor MnU switches off; in this way, charge sharing is obtained between the two pump capacitors Cd, adjacent to one another, connected to the second internal nodes Di−1, Di, whereas charge sharing between the two pump capacitors Cu, connected to the first internal nodes Ui−1, Ui is prevented (note that by “charge sharing” is meant a transfer of charge from the previous stage to the next);        FN=0, FX=Vdd: in this case, the circuit operates in a way altogether similar to the previous situation, with the difference that charge sharing occurs between the two pump capacitors Cu connected to the first internal nodes Ui−1, Ui (in other words, charge transfer involves the top branch of the circuit).        
Advantageously, during the two half-periods in which the control nodes PgD, PgU, NgD, NgU go to a high or a low level, the same control nodes remain, throughout charge sharing, always at a substantially constant voltage, of a value such as to enable an effective switching-on, or switching-off, of the latch transistors connected thereto (in other words, any fluctuation in the logic supply voltage Vdd is prevented from possibly jeopardising switching-on/switching-off of the transistors). The control transistors Mp1, Mp2, Mn1, Mn2 enable the capacitances of the biasing capacitors Cb1, Cb2, Cb3, Cb4 to be updated to the voltage of the nodes to which they refer and to recover the charge lost for driving the respective latch transistors. The biasing capacitors hence act as “bootstrap” capacitors, effectively driving the gate terminals of the latch transistors.
In particular, even in the case where the logic supply voltage Vdd is particularly low, for example equal to 1 V, the charge pump circuit 1 continues to operate properly, unlike, for example, the circuit of FIG. 1, where instead, the internal nodes Di, Ui may vary their voltage value during the various half-periods (being directly connected to a pump capacitor), up to possibly preventing the corresponding pass transistors from switching on.
FIG. 3 shows the values of some voltages internal to the charge pump circuit 1 during the half-period in which charge sharing takes place between the pump capacitors Cd, adjacent to one another, connected to the second internal nodes Di−1, Di. In particular, it may be noted that the voltages at the control nodes PgD, NgD remain substantially constant during the entire half-period (for example, they do not have a variation of more than 4-6%).
The charge pump circuit 1 of FIG. 2 has several advantages, and in particular enables, using only low voltage transistors, operation at high frequency (for example up to 150 MHz) with good electrical performance. However, the same circuit has a drawback, principally linked to the area occupation (in the integrated implementation on silicon) and to the current consumption.
In this regard, it should be noted that the “pumping” capacitance of the charge pump circuit 1 is given by the following expression:
  C  =            N      ·              I        L                            [                                            (                              N                +                1                            )                        ·            Vdd                    -          Vout                ]            ·      f      
where N is the number of stages of the pump; IL is the current supplied to the load; Vdd is the logic supply voltage (for example, the internal supply voltage of the memory in which the charge pump circuit 1 is used); Vout is the output voltage of the charge pump circuit 1; and f is the clock frequency (which determines the periodicity of operation of the circuit).
Moreover, the current consumption of the charge pump circuit 1, i.e., the current required by the power supply (which supplies the voltage Vdd) is given by the following expression:I(Vdd)={(N+1)+α·[N2/(N+1)·Vdd−Vout]·Vdd}·IL where α is the ratio between the value of the parasitic capacitance of the circuit and the value of the pumping capacitance defined previously.
It may thus be appreciated that, if supply voltages of a low value (for example, 1 V) are used for operation, then the need arises to have higher pumping capacitances and a greater number of stages in the charge pump circuit to reach desired values for the output voltage and the current supplied to the load; in turn, this involves a larger area occupation and a higher current consumption.
It should be noted that, given that it is necessary in all cases to satisfy the specifications of current required by the load, the charge pump circuit is in general sized at the minimum supply voltage; it follows that the problem highlighted above is particularly felt.